• Early Verification IP Developer for Rev3.0/Rev2.0
  • Patent pending completely Configurable and Scalable architecture
  • Supports Real Time System Level Scenarios
  • Fully customizable Power Management, Battery System Models
  • Flash Model, UART, SPI, and I2C BFMs enabling system level verification
  • USB Device Power States support
  • Exhaustive test suite, error suite checkers and coverage
  • Plug-Play integration into any IP or SOC environment
  • Gate Level and Power Aware Simulations support
  • FPGA proven Verification IP


  • Fully configurable multi-port Verification IP and Testbench using SV/UVM
  • Behavior models (BMOD) for CC and PD PHY, VBUS Power Management and Battery System
  • Exhaustive sanity and error case test-suite along with reusable configurations and pre-enabled callback library
  • Built-in compliance checkers and coverage
  • Comprehensive Verification Plan and User guide
  • VIP Integration and Simulation DEMO Video along with Integration guide
  • Transaction Level protocol tracker for easy debug

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